1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the initiation of exception processing within data processing systems in response to the occurrence of an exception condition.
2. Description of the Prior Art
It is known to provide data processing systems with exception handling mechanisms. As an example, the processors designed by ARM Limited, Cambridge, England are responsive to external interrupt signals and exception and abort conditions to trigger exception processing. Such exception processing in this example system involves a switch of processor state into an exception handling mode with the existing state being saved. An exception vector is associated with the jump to the exception handling mode and serves to point to an exception handling routine. When the exception has been processed, exception handling is terminated and a switch is made back to the original mode with the original context being restored.
An important characteristic of many data processing systems, such as real time data processing systems, is their interrupt latency. In some systems it is critical that the system responds to an interrupt condition as quickly as possible. As an example, in an automotive application, a processor controlling an anti-lock braking system may need to respond rapidly to an interrupt signal indicating occurrence of a dangerous condition and the associated interrupt latency is the maximum time taken to initiate processing of the interrupt under all conditions. The interrupt latency assumes the worst-case in which the initiation of interrupt processing will be delayed for the longest time. Measures which can increase the speed of initiation of interrupt processing and reduce the interrupt latency are strongly advantageous.
It is know within high performance data processors to utilise a technique termed branch prediction. With this technique, branch instructions occurring in a program instruction stream are recognised before they are executed within the instruction pipeline and a prediction is made as to whether or not the branch involved will or will not be taken. The instruction prefetch unit is responsive to this prediction to fetch subsequent instructions from either the next following memory location or from the branch target location. If the prediction is correct, then this saves time as the correct instructions will have been prefetched and loaded into the instruction pipeline. The alternative may be, for example, that a branch instruction proceeds along the pipeline with following instructions being prefetched sequentially. When that branch instruction is reached and executed, the branch is taken and it is found that the incorrect instructions have been prefetched into the instruction pipeline requiring these incorrect instructions to be flushed out and a time penalty incurred due to the fetching of the correct instructions from the branch target. The branch instruction may be removed from the instruction stream when its behaviour has been predicted with a check being made to ensure that the conditions associated with the prediction did occur at the point at which the branch instruction would have been executed.